OZAYR RAAZI

Ozayr Raazi in Yosemite
expand_more

Salam! My name is Ozayr

I'm a fourth-year Computer Engineering student at the University of Waterloo. I am passionate about all things tech-related, with a special interest in firmware, embedded systems, PCBs, FPGAs, and computer architecture.

Currently, I'm on a co-op term at Astera Labs in San Jose, and I graduate in April 2027!

Ozayr Raazi

Projects

ECE Capstone · In progress

Sage: Offline AI Voice Assistant

  • Leading a 6-person team building a fully offline voice assistant from a Raspberry Pi 5 host and an Artix-7 FPGA LLM accelerator connected over PCIe; defined the system architecture and requirements
  • Developed the C++ host pipeline (audio capture, whisper.cpp speech-to-text, llama.cpp LLM, Piper text-to-speech) with a real-time SCHED_FIFO audio thread and an orchestrator state machine
  • Wrote the Pi-to-FPGA PCIe/XDMA driver layer and the interface spec (register map, DDR3 memory layout, data formats) both teams build against; validated the link on hardware at Gen2 x1 with 1.29 µs register round trips
  • As lead reviewer of the PCIe adapter PCB carrying the Pi-to-FPGA link, caught a pinout error and a differential pair length mismatch before the board went to fabrication
C++ PCIe FPGA Raspberry Pi Project Management
Sage System Block Diagram

PCB · Team project

Biro-1

  • Ideated and planned a fully-custom media controller device to address a real-world need of keyboard not having hardware media keys, and created a team of 5 people to help realize the project
  • Defined product requirements, set timelines, organized subsystems, and created high-level tasks for delegation among team members
  • Researched components, designed block and schematic diagrams, and started layout for prototype board, while assisting in firmware and RTOS development
Clickable GitHub Icon KiCAD PCB Design C++ Project Management
Printed Circuit Board

FPGA · Digital Hardware Systems course

MVM Engine + Tanh Circuit

  • Implemented the Matrix-Vector Multiplication engine from Microsoft's Project Brainwave deep learning accelerator, including pipelined dot-product and accumulator modules, and a control FSM
  • Built a fully pipelined tanh activation circuit (Taylor approximation) for neural networks, optimized to run at 561 MHz on a Pynq-Z1 FPGA using DSP48E1 slices
SystemVerilog AMD Vivado Digital Design
MVM Diagram

More Projects

Assembled Spidey Sense PCB

PCB

Spidey Sense

Thermocouple-to-4-20mA PCB for Waterloo Rocketry engine tests, designed in KiCAD and hand-assembled

KiCAD PCB Design Soldering
Simulated CPU Picture

Digital Logic

8-Bit CPU

8-bit CPU built from logic gates with a custom 34-instruction ISA, assembler, and 6-cycle fetch/execute

Logisim Assembly Python
Omnibus Dashboard Picture

Software

Omnibus

Waterloo Rocketry data bus and dashboard in Python; rewrote the dashboard and cut startup time by 67%

Python PyQtGraph
Custom RC Car Picture

Embedded

Sand Crab

Arduino RC car with a 3D-printed claw and nRF24L01 2.4 GHz radio remote

Arduino 3D Printing
6-rotor Drone Picture

Electronics

Hexacopter Drone

6-rotor drone on a DJI Naza M2 flight controller; wired GPS, telemetry, and video, then rebuilt it after a crash

DJI 3D Printing
Desktop Computer Picture

Homelab

Personal NAS

Unraid NAS from an old PC hosting backups, a document cloud, Pi-hole, and Git

Docker Unraid

Experience

Astera Labs

Hardware Diagnostics Engineer (Co-op)

Sept. 2026 - Present

Hardware Diagnostics Engineer (Co-op)

C | Python | Thermal Control | Manufacturing Test

  • Scaled the thermal control loop from one product to 5 product variants and integrated it into manufacturing tests
  • Created a temperature calibration curve deriving a customer-required reading from an internal sensor to within 2°C, meeting a spec that previously needed custom external test equipment
  • Built a mock of an unreleased system from existing boards and adapted firmware/tools to target it, enabling software development before hardware arrived and validating a configuration no current system supports

Astera Labs

Hardware Diagnostics Engineer (Co-op)

Jan. 2026 - April 2026

Hardware Diagnostics Engineer (Co-op)

C | Python | Raspberry Pi | I2C

  • Cut uncaught production-line errors from 0.26% to 0.01% by isolating I2C communication failures and porting the subtest from Python to C
  • Led bring-up and validation of evaluation boards for 2 high-speed retimer ASICs, writing low-level C utilities on Raspberry Pi hosts that extended diagnostics to new ICs, sensors, power rails, and fans
  • Developed a thermal control loop to hold modules at a target temperature during testing, using a Proportional-Integral controller with feedforward and a custom YAML parser

Untether AI

Hardware Engineer (Co-op)

Jan. 2025 - April 2025

Hardware Engineer (Co-op)

PCB | Cadence OrCAD X | STM32

  • Designed 4-layer evaluation Printed Circuit Board from scratch using Cadence OrCAD X, including component research, schematic diagram, and layout, to evaluate new Power-Management ICs
  • Verified functionality of 40+ AI Accelerator Cards by conducting physical inspections, short checks, performance benchmarks, and neural network correctness tests, while ensuring power/thermal compliance
  • Reduced current sensing IC's error from 8% to <1% by sweeping configuration registers and comparing current values measured via STM32 to adjustable current load's readout, simulating an active board

Untether AI

Firmware Engineer (Co-op)

May 2024 - Aug. 2024

Firmware Engineer (Co-op)

C | RISC-V | I2C/PMBus | UART/JTAG | OpenOCD

  • Wrote bare-metal C firmware, shipped on customer cards, for the RISC-V core of an AI Accelerator Card (PCIe Gen5 x16) ASIC: power sequencing, temperature sensing, power monitoring, and fan control over I2C and PMBus
  • Brought the first batch of accelerator cards to full boot in under 3 days by flashing PMICs, power sequencers, and ASICs, and debugging over UART/JTAG, unblocking higher-level software teams
  • Researched and proposed switching a voltage rail from single-phase to dual-phase, projecting a 46% reduction in power loss and 10% higher efficiency; the change was adopted

Ciena

Embedded Software Engineer (Co-op)

Sept. 2023 - Dec. 2023

Embedded Software Engineer (Co-op)

C/C++ | GoogleTest | LibEvent

  • Accelerated iteration and testing of a Segment-Routing module by developing an event-based client for simple user interfacing and by configuring CMAKE to enable independent compilation
  • Improved error-detection of a TCP-transport library by creating C++ GoogleTest unit tests, allowing for send and receive functionalities to be tested concurrently using multi-threading
  • Increased thread safety of C code and protected internal data structures by converting APIs to signal-based

Dell

Software Engineer (Co-op)

Jan. 2023 - April 2023

Software Engineer (Co-op)

Python | Jenkins | Coverity | qTest | Docker

  • Enhanced security of a PCIe card by implementing Trusted Boot features such as allowing binary signing without access to private RSA keys
  • Eliminated the need for physical boards for initial firmware testing by configuring an ARM emulator
  • Improved testing capabilities by increasing the number of automated tests running in Docker containers, creating new Robot Framework software robots
  • Boosted software security by enabling fast discovery of potential vulnerabilities by creating Jenkins CI pipelines to run code analysis using Coverity

Waterloo Rocketry

Software Subsystem Lead

Sept. 2022 - Sept. 2024

Software Subsystem Lead

Python | C | KiCAD

  • Contributed to a team of 60+ people for the annual development and launch of a rocket to 30,000 ft
  • Increased organization in the Software subsystem by creating a GitHub Project board for issue tracking and by adding branch naming conventions, PR templates and repository Codeowners
  • Facilitated development by onboarding new members, breaking down projects into individual issues, creating and maintaining timelines, supporting developers, and reporting progress to team leads
  • Augmented data collection capabilities for engine tests and added support for thermocouples by creating electrical schematics and designing PCBs using KiCAD
  • Optimized Kalman filter for estimating rocket position during flight by developing C code to convert coordinates between reference frames using rotation matrices

Education

University of Waterloo

Honours Computer Engineering

Sept. 2022 - April 2027

Computer Engineering Student

  • Program: Honours Computer Engineering
  • Expected Graduation: April 2027
  • Relevant Courses:
    • ECE 493: Machine Learning Hardware Systems
    • ECE 320: Computer Architecture
    • ECE 722: Reconfigurable Computing (Graduate-level)
    • ECE 327: Digital Hardware Systems
    • ECE 350: Real-Time Operating Systems
    • ECE 340: Electronic Circuits 2

Skills

Languages

  • C/C++
  • Python
  • Bash
  • Verilog/SystemVerilog
  • VHDL
  • RISC-V/ARM Assembly

Embedded

  • STM32
  • Raspberry Pi
  • I2C
  • PMBus
  • UART
  • JTAG
  • PCIe

Hardware

  • Oscilloscope
  • Logic Analyzer
  • Cadence OrCAD X
  • KiCAD
  • Fusion Digital Power

FPGA & Tools

  • AMD Vivado
  • Intel Quartus
  • Verilog-To-Routing (VTR)
  • GDB/LLDB
  • OpenOCD
  • Git
  • Linux